Correlated double sampler (CDS) circuits are used extensively in CCD imaging systems for both scientific and commercial imaging systems. Testing a CDS circuit and characterizing it for linearity at high resolutions and speeds is a challenging task, touching the limits of existing technology. This is especially true with the introduction of 12-bit frontends for CCD imaging systems at speeds up to 21-MSPS for the commercial end equipment market. The task is complicated by the way a CDS is required to sample its input, the CCD waveform as shown at 10 in FIG. 1.
The CDS samples at two different points t1 and t2 separated at a fixed distance in time T at a given rate. Thus, in each cycle of the input waveform, the CDS is required to sample at two given points in time and give an output proportional to the difference in the voltage levels at these two points. These two points correspond to the reset level 12 of the signal and the video level 14 of the signal. The output in this case was given to an internal 14-bit ADC and the ADC digital output was checked for linearity using static tests.
Testing such a circuit for linearity requires an input voltage waveform with two accurate and known levels at two given time points at the given repetition frequency. Moreover, the voltage level of this waveform should be accurate to at least a couple of LSBs more than the resolution of the CDS, so that the overall performance is limited by the CDS rather than by the input source. In addition, this waveform requires the video level to be changing in a discrete ramp fashion from cycle to cycle so that what we see at the CDS output would be a ramp. This aids in conveniently figuring the CDS linearity, conventionally performed using a simple histogram technique.
But, this ramp “modulation” also presents the greatest challenge in generating such a waveform. Other methods may involve input sources other than the exact waveform previously described and indirect interpretation of the accrued results. Additional constraints imposed by the nature of the CDS input circuitry and requirements arising from the limitations of the CDS input circuit further complicate the test process.
Although it is possible to do away with such special waveform requirements by including a sample-and-hold type test circuit in the CDS, this disrupts the normal functioning of the CDS. This introduces additional unwanted parasitic elements in the signal path, which is not desirable for such a high-resolution system.
Schemes also exist where the test-mode input pins to the CDS are brought out separately through the required additional components. But these schemes are unsatisfactory in that they do not test the actual signal path on which the CDS operates. They also require additional pins on the package.
There is desired a methodology of testing the CDS linearity at high resolution and high speed while aiming for the minimum test cost. The testing method should be repeatable and worthy of production testing.